This invention relates to switching circuit techniques such as output circuit techniques, and further to circuit techniques which are particularly effective when applied so as to drive a d.c. load in circuits such as those employing TTL. The present invention relates to a technique which can be effectively utilized for a buffer circuit producing a CMOS logic level at the TTL level in a Bi-CMOS type (bipolar/CMOS mixed type) gate array, for example.
H. C. Lin et al disclose Bi-CMOS type inverters and logic gates of the kind described above in the reference "IEEE TRANSACTIONS ON ELECTRON DEVICES", Vol. ED-16, No. 11, November 1969, p.p. 945-951. The Bi-CMOS type inverter disclosed by H. C. Lin et al includes an output stage consisting of a pair of bipolar transistors connected in series in a totem pole arrangement, and a pre-stage circuit consisting of a p-channel MOS field effect transistor and an n-channel MOS field effect transistor. The gates of both MOS field effect transistors of the pre-stage circuit are driven in common by a single input signal. The drain output of the p-channel MOS field effect transistor is applied to the base of one of the bipolar transistors, and the source output of the n-channel MOS field effect transistor is applied to the base of the other transistor of the output stage. An output signal having a phase opposite to that of the input signal can thus be obtained from the common junction of the pair of transistors.
Therefore, the Bi-CMOS type inverter of H. C. Lin at al can accomplish low standby power as well as large driving capability.
Five inventors among the inventors of the present application invented previously a high speed, low power consumption Bi-CMOS type semiconductor integrated circuit having the construction in which an internal logic circuit is operated at a CMOS level, the output transistor in a peripheral circuit as an input level converter or an output level converter consists of a bipolar transistor, and this output transistor charges or discharges the output capacity of the peripheral circuit (Japanese Patent Application No. 12711/1983, U.S. patent application No. 575,567, British Patent Application No. GB 2,135,148A, West German Patent Application No. P 34 03 276.2 and Korean Patent Application No. 1983-5666).
The output stage of the output buffer circuit used as the peripheral circuit described above consists of bipolar transistors so that the "L" (low level) logic level can be kept below a predetermined level even when a large number of TTLs are connected to its output, that is, in order to obtain large fan-outs.
FIG. 1 shows the output buffer circuit 10 invented by the five inventors among the inventors of the present invention prior to the present invention.
The buffer circuit 10 shown in the drawing is arranged so that its logic output can assume a high impedance floating condition in addition to the binary logic stage of "H" (high level) and "L" (low level). In other words, the logic circuit 10 is constructed in a "tri-state" configuration, and can therefore be used by connecting it to the signal bus of a micro-computer system, for example.
Its circuits construction is based upon that of TTL, and its output stage consists of a pair of bipolar transistors Q1 and Q2 connected in series in a totem-pole arrangement between the power source Vcc and the ground potential, a resistor R1, and the like. The buffer output can be taken out from the intermediate junction of the pair of bipolar transistors Q1 and Q2. Another bipolar transistor Q4 is Darlington-connected to the base of one of these bipolar transistors (e.g. Q1).
A pre-stage circuit for complementarily driving the pair of bipolar transistors Q1 and Q2 consists of a phase spliting circuit consisting in turn of a bipolar transistor Q3 and a resistor R2, and an input circuit consisting of an n-channel MOS field effect transistor M1 and a resistor R3. The buffer input IN is connected to the gate of the field effect transistor M1. A bipolar transistor Q5 and resistors R4 and R5 are also disposed in order to extract the base residual charge of the bipolar transistor Q2 of the output stage.
The circuit arrangement described above can convert a CMOS level logic signal from an internal circuit 20 consisting of a CMOS logic circuit, for example, to a high driving capability logic signal of the TTL level and can produce the latter as an output.
Furthermore, an enable control circuit 30 is added to the buffer circuit 10 so that it can operate as a tri-state buffer circuit. The enable control circuit 30 consists, for example, of a bi-polar transistor Q30 subjected to switching control by an enable signal EN generated by the internal circuit 20, for example, diodes D30 and D31, and so forth. When the enable signal EN is "H" in this circuit 30, the n-channel field effect transistor M0 is turned ON (becomes conductive) while the transistors Q20 and Q30 are turned OFF (becomes non-conductive, so that the output OUT of the output buffer circuit 10 is under the active condition in which it takes either one of the two logic states "H" and "L" in response to the buffer input IN. When the enable signal EN becomes "L", the transistor Q30 is turned ON (becomes conductive), whereupon the collector and base current of the transistor Q3 of the phase splitting circuit are forcibly bypassed through the paths of the diodes D30 and D31 and the transistor Q30 (represented by solid line), both transistors Q1 and Q2 of the output stage are turned OFF irrespective of the stage of the buffer input IN, and the output OUT is in a floating condition, that is, in the high impedance condition. Thus, the output OUT of the buffer circuit 10 is rendered non-active.
As described above, the buffer circuit can operate as a tri-state buffer circuit. When its output OUT is connected to the signal bus inside a micro-computer system, for example, electric connection state with respect to the signal bus can be freely controlled by the enable signal.
However, the inventors have clarified the fact that in accordance with the technique described above, the operating current of the pre-stage circuit is forcedly bypassed by the diodes D30, D31 and the transistor Q30 to render the output OUT high impedance, and so long as the output OUT is kept at the high impedance, a d.c. current flows through the transistors Q20 and Q30 and the power consumption or so-called standby power becomes inevitably great.